precision audio clock source ics661 mds 661 d 1 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com precision audio clock source description the ics661 provides synchronous clock generation for audio sampling clock rates derived from an mpeg stream, or can be used as a standalone clock source with a 27 mhz crystal. the device uses the latest pll technology to provide excellent phase noise and long term jitter performance for superior synchronization and s/n ratio. please contact ics if you have a requirement for an input and output frequency not included here - we can rapidly modify this product to meet special requirements. features ? packaged in 16-pin tssop ? available in pb (lead) fere package ? clock or crystal input ? low phase noise ? low jitter ? exact (0 ppm) multiplication ratios ? reference clock output available ? support for 256, 384, 512, and 768 times sampling rate block diagram pll clock synthesis selin crystal oscillator x2 x1/refin vdd (p2) vddr ref clk gnd (p13) gnd (p6) gnd (p5) s3:0 4 vdd (p3) vddo idt? / ics? precision audio clock source ics661 1 data sheet ics661
idt? / ics? precision audio clock source ics661 2 ics661 precision audio clock source tsd precision audio clock source mds 661 d 2 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics661 pin assignment 16-pin 4.40 mil body, 0.50 mm pitch tssop output clock selection table pin descriptions 12 1 11 2 10 x1/refin x2 3 9 vdd 4 vdd ref 5 s0 6 vddr 7 gnd 8 gnd gnd selin vddo s3 s1 s2 clk 16 15 14 13 s3 s2 s1 s0 input frequency (mhz) output frequency (mhz) 0000 27 8.192 0001 27 11. 2896 0010 27 12.288 0011 27 24.576 0100 27 12.288 0101 27 16. 9344 0110 27 18.432 0111 27 36.864 1000 27 16.384 1001 27 22. 5792 1010 27 24.576 1011 27 49.152 1100 27 24.576 1101 27 33. 8688 1110 27 36.864 1111 27 73.728 pin number pin name pin type pin description 1 x1/refin input connect this pin to a crystal or clock input 2 vdd power power supply for crystal oscillator. 3 vdd power power supply for pll. 4 s0 input output frequency selection. determines output frequency per table above. on chip pull-up. 5 gnd power connect to ground. 6 gnd power ground for output stage. 7 s3 input output frequency selection. determines output frequency per table above. on chip pull-up. 8 s2 input output frequency selection. determines output frequency per table above. on chip pull-up. 9 clk output clock output. 10 s1 input output frequency selection. determines output frequency per table above. on chip pull-up. 11 vddo power power supply for output stage. 12 selin input low for clock input, high for crystal. on chip pull-up. 13 gnd power connect to ground. 14 vddr power power supply for reference output. ground to turn off ref. 15 ref output reference clock output. 16 x2 input connect this pin to a crystal. leave open if using a clock input.
idt? / ics? precision audio clock source ics661 3 ics661 precision audio clock source tsd precision audio clock source mds 661 d 3 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics661 application information series termination resistor clock output traces should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitors as with any high performance mixed-signal ic, the ics661 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. to further guard against interfering system supply noise, the ics661 should use one common connection to the pcb power plane as shown in the diagram on the next page. the ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. recommended power supply connection for optimal device performance all power supply pins must be connected to the same voltage, except vddr and vddo may be connected to a lower voltage in order to change the output level. if the reference ou tput is not used, ground vddr. crystal load capacitors if a crystal is used, the de vice crystal connections should include pads for capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. to reduce possible noise pickup, use very short pcb traces (and no vias) been the crystal and device. the value of the load capacitors can be roughly determined by the formula c = 2(c l - 6) where c is the load capacitor connected to x1 and x2, and c l is the specified value of the load capacitance for the crystal. a typical crystal c l is 18 pf, so c = 2(18 - 6) = 24 pf. because these capacitors adj ust the stray capacitance of the pcb, check the output frequency using your final layout to see if the value of c should be changed. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) the external crystal should be mounted next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi and obtain the best signal integrity, the 33 ? series termination resistor should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the ics661. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. connection to 3.3v power plane ferrite bead bulk decoupling capacitor (such as 1 f tantalum) vdd pin vdd pin vdd pin 0.01 f decoupling capacitors
idt? / ics? precision audio clock source ics661 4 ics661 precision audio clock source tsd precision audio clock source mds 661 d 4 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics661 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics661. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c item rating supply voltage, vdd 5.5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v vddo 1.8 vdd v vddr 1.8 vdd v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -20 ma 2.4 v output low voltage v ol i ol = 20 ma 0.4 v supply current idd no load 25 ma short circuit current i os each output 65 ma nominal output impedance z out 20 ? input capacitance input pins 7 pf internal pull-up resistor 120 k ?
precision audio clock source mds 661 d 5 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics661 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c thermal characteristics parameter symbol conditions min. typ. max. units crystal frequency 27 28 mhz output clock rise time t or 20% to 80%, 15 pf load 1.5 ns output clock fall time t of 80% to 20%, 15 pf load 1.5 ns output duty cycle t od at vdd/2, 15 pf load 45 49 to 51 55 % jitter, short term reference clock off 175 ps p-p jitter, short term reference clock on 175 ps p-p jitter, long term reference clock off; 10 us delay 300 ps p-p jitter, long term reference clock on; 10 us delay 300 ps p-p single sideband phase noise reference clock off; 10 khz offset -110 dbc single sideband phase noise reference clock on; 10 khz offset -110 dbc actual mean frequency error versus target 0ppm parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w idt? / ics? precision audio clock source ics661 5 ics661 precision audio clock source tsd
idt? / ics? precision audio clock source ics661 6 ics661 precision audio clock source tsd precision audio clock source mds 661 d 6 revision 111804 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics661 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics661gi ics661gi tubes 16-pin tssop -40 to +85 c ics661gitr ics661gi tape and reel 16-pin tssop -40 to +85 c ICS661GILF 661gilf tubes 16-pin tssop -40 to +85 c ICS661GILFtr 661gilf tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
ics661 precision audio clock source tsd ics9148-53 frequency generator & integrated buffers for mother boards tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com sd0060cn02270t 60.00 mhz differential delay line for commercial applications tsd
|
